1. Field of the Invention
The present invention relates generally to a method for reading, and a data reading apparatus for a disk drive apparatus, and more particularly, to an apparatus and method for detecting and reading a sync pattern or an address mark within data recorded on a recording medium by a pulse width modulation (PWM) system.
2. Description of the Related Art
Higher density is in demand for recording media such as magneto-optic disks. In this respect, pulse width modulation (PWM) systems for recording data on a recording medium have been receiving more widespread attention than the conventional Pit Position Modulation (PPM) system.
Conventionally, a typical system for recording data on a recording medium such as an optical disk is pit position modulation (PPM). In a PPM system, when one-byte of data, for example, "0, 1, 0, 1, 0, 1, 0, 1" is to be recorded on a recording medium, a plurality of recording areas have to be secured in association with the individual bits of that one-byte of data. The data pertaining to the individual bits are stored in the associated recording areas. Upon reading the one-byte of data from a recording medium, a drive head sequentially seeks the recording areas associated with the individual bits, thereby obtaining the one-byte of data. In a PPM system, it is required to secure a single recording area for a single bit.
One way to increase and, therefore, improve the recording density in a recording medium is to narrow or shorten the width of a recording area for one bit. As the width of each recording area is narrowed, a higher recording density is ensured, but the period of waveforms of signals provided from the drive head become shorter. Additionally, in order to narrow the width of each recording area, it is required to decrease the spot size of an optical pickup device which constitutes the drive head. The requirements on processing signals by a signal processing circuit are such that either, the sampling period should be made shorter, or the spot size should be made smaller. Therefore, there is a limit to improving the recording density of a medium by narrowing the widths of recording areas.
A great deal of attention is paid to using a PWM system as an approach to improve the recording density in a recording medium. In the case of recording one byte of data on a recording medium in accordance with a PWM system, for example, all of the bits lying between a bit indicative of "1" and a subsequent bit indicative of "1" are regarded as indicating "0".
Referring to FIG. 1, the difference between a PWM system and the conventional PPM system will be described in more detail. FIG. 1 shows a waveform RD.sub.PPM of data D1, read by the drive head from a recording medium in which the data D1 has been recorded following the conventional PPM system, and a waveform RD.sub.PWM of data D1, read by the drive head from a recording medium in which the data D1 has been recorded following the PWM system.
In the PPM system, data of "1" is all represented as a signal waveform with a high potential level (i.e., an H level), while data of "0" is all represented as a signal waveform with a low potential level (i.e., an L level).
In contrast, according to the PWM system, every time a bit with data of "1" is read, the potential level of the signal waveform RD.sub.PWM is inverted. The signal waveform rises to the H level at the fourth bit having data of "1", and falls to the L level at the seventh bit having data of "1", as shown in FIG. 1. The signal waveform rises again to the H level at the eleventh bit having data of "1", and falls to the L level at the thirteenth bit having data of "1". Likewise, the signal waveform rises to the H level at the nineteenth bit having data of "1", falls to the L level at the twenty-second bit having data of "1", rises again to the H level at the twenty-fourth bit having data of "1", and falls to the L level at the twenty-sixth bit having data of "1".
In other words, unlike the PPM system, the PWM system does not need to secure a single recording area on a recording medium for a single bit. As mentioned above, the PWM system recognizes all of the bits lying between a first bit with data of "1" and a second bit with data of "1" as having data of "0". Accordingly, the period of the signal waveform RD.sub.PWM of the data D1 read according to the PWM system is longer, at any point in time, than the period of the waveform RD.sub.PPM of data D1 read according to the PPM system. Considering the characteristics of a PWM type recording medium and a PPM type recording medium, the width of the recording area required per bit may be set to be more narrow by the PWM system in which a single recording area can be assigned for a plurality of consecutive bits, compared with the PPM system in which a single recording area is required for a single bit. Accordingly, the PWM system is more advantageous than the PPM system when it comes to increasing the recording density on a recording medium.
Furthermore, the PPM system differs from the PWM system as to how one byte of data is recorded in a user data section in each sector on a recording medium. According to the PPM system, one byte of data input by a user is converted into data of 16 channels (two bytes), with reference to a previously prepared conversion table, and the 16 channel data are in turn recorded in a user data section of a sector. In contrast, according to the PWM system, one byte of data input by a user is converted to data of 12 channels (1.5 bytes), with reference to a previously prepared conversion table, and the 12 channel data are in turn recorded in a user data section of a sector. In this respect, the PWM system has once again been shown to be more advantageous than the PPM system in the area of increasing the recording density on a recording medium.
The act of reading data, recorded on a recording medium by the PWM system, is executed by a signal processing circuit in a manner as described below. When data D1 as shown in FIG. 2 is read by a drive head, the signal waveform RD.sub.PWM of the read data D1 has a rectangular waveform. The rising edge (i.e., leading edge) and falling edge (i.e., trailing edge) of the signal waveform RD.sub.PWM are detected by a detecting circuit (e.g. comparator) coupled to the drive head. Assuming that the H level and the L level of the waveform RD.sub.PWM are set to 5 volts and 0 volts, respectively, for example, a reference voltage V.sub.ref is set to 2.5 volts. The comparator compares the potential level of the signal waveform RD.sub.PWM with the reference voltage V.sub.ref. When the potential level of the signal waveform RD.sub.PWM exceeds the reference voltage V.sub.ref, the potential level is regarded as a H level. When the potential level of the signal waveform RD.sub.PWM is equal to or lower than the reference voltage V.sub.ref, the potential level is regarded as a L level. When the potential level of the output from the comparator is inverted, i.e., when a leading edge or trailing edge is detected, it is determined that a bit with data of "1" has been read. As long as the output of the comparator is not inverted, i.e., as long as neither a leading edge nor a trailing edge is detected, it is determined that bits having data of "0" are being read at a predetermined sampling period.
The signal waveform RD.sub.PWM of the drive head may unfortunately vary in its potential level either due to noise originating from DC signal components, or due to the signal waveform RD.sub.PWM becoming dull. The variation in the potential level becoming of RD.sub.PWM is such that the L and H levels of the waveform RD.sub.PWM do not become 0 volts and 5 volts, respectively, and the potential level of the whole signal waveform generally varies so that an offset voltage is temporarily generated. The dull waveform means that the waveform RD.sub.PWM is not a rectangular waveform, and the rising and falling of the signal is very gradual due to a fast reading speed.
Generally speaking, data D2, which is recorded in a lockup pattern section (VFO section) provided in each of sectors on a recording medium, contains "0" and "1" arranged alternately, as shown in FIG. 3. When a drive head reads the data D2 from a recording medium in which data have been recorded in accordance with the PWM system, the signal waveform RD.sub.PWM of the read data D2 has a form as shown in FIG. 3. In other words, even if recording has been done with the PWM system, the read waveform RD.sub.PWM begins to approximate a sine wave. If DC component noise is superimposed on the signal waveform RD.sub.PWM, the entire waveform RD.sub.PWM varies in accordance with the strength of the DC noises.
FIG. 4 shows a signal waveform RD.sub.PWM containing a DC component. If the leading and trailing edges of the waveform RD.sub.PWM are determined with reference to a single reference voltage V.sub.ref, the data D2 may be erroneously read out. Even when the voltage potential level of the entire waveform RD.sub.PWM changes, the reference voltage does not change accordingly. In FIG. 4, L1 indicates an interval from a leading edge to a trailing edge of an unchanged section in which the potential level of the signal waveform is appropriate, while L2 indicates an interval from a leading edge to a trailing edge of a changed section in which the potential level of the signal waveform varies. The interval L1 differs from the interval L2. The difference between the intervals L1 and L2 is reflected as the difference in the number of bits having data of "0" lying in the intervals L1 and L2. Specifically, when the interval L2 is longer by one bit than the interval L1, the data in the interval L1 will be correctly determined as "101" but the data in the interval L2 will be erroneously determined as "1001", because of the constant sampling period.
To avoid such erroneous determinations, the leading edge and trailing edge can be separately detected by using a first reference voltage to detect a leading edge, V.sub.ref1, and a second reference voltage to detect a trailing edge, V.sub.ref2. FIG. 5 shows the relationship between the waveform RD.sub.PWM shown in FIG. 4 and the first and second reference voltages V.sub.ref1 and V.sub.ref2. Even in this case, there is a difference between the interval L1 and the interval L2. However, an interval L3 from a leading edge to the next leading edge is substantially the same as an interval L3 in the normal case in which the signal waveform has an appropriate voltage potential level, while an interval L4 from a trailing edge to the next trailing edge is substantially the same as an interval L4 in the normal case. Therefore, the use of two reference voltages V.sub.ref1 and V.sub.ref2 prevents the number of "0" data bits from being erroneously determined as greater than a correct number, thereby allowing for correct data reading.
The edge detection with two reference voltages V.sub.ref1 and V.sub.ref2 is executed by a signal processing circuit 80 provided with first and second signal processors 81 and 82, as shown in FIG. 6. The first signal processor 81 receives data RD.sub.PWM read by a drive head 83 from an optical disk 84 on which data is recorded in accordance with the PWM system, and detects leading edges of a waveform of the read data RD.sub.PWM with reference to the first reference voltage V.sub.ref. When a leading edge is detected on the waveform RD.sub.PWM, the first signal processor 81 outputs bit data indicative of "1". The first signal processor 81 also outputs a plurality of pieces of bit data indicative of "0" and determines the number of data "0" based on the sampling periods between consecutive leading edges.
Likewise, the second signal processor 82 receives the read data RD.sub.PWM output from the drive head, and detects trailing edges of the waveform RD.sub.PWM with reference to the second reference voltage V.sub.ref2. When a trailing edge is detected on the waveform RD.sub.PWM, the second signal processor 82 outputs bit data indicative of "1". The second signal processor 82 also outputs a plurality of pieces of bit data indicative of "0" and determines the number of data "0" based on the sampling periods between consecutive trailing edges.
Referring to FIG. 7, data DTLE and DTTE of the two signal processors 81 and 82 will be described.
When data D2 in a lockup pattern section of a sector is: EQU "0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, . . . ",
the first signal processor 81 outputs data DTLE as follows: EQU "0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, . . . ", and
the second signal processor 82 outputs data DTTE as follows: EQU "0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, . . . ".
The data DTLE and DTTE are supplied to a disk controller 85, which acquires their logical sum in order to yield the data D2 in the lockup pattern section.
In order to combine the two data DTLE and DTTE of the two signal processors 81 and 82 to produce the data D2 in a lockup pattern section, however, the output timings for the data DTLE and DTTE should be synchronized with each other.
For example, there may be a case where the data DTTE from the second signal processor 82 is output faster by one bit data than the data DTLE, such that the data DTTE is as follows: EQU "0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, . . . ".
In this case, the execution of a logical sum between DTTE and DTLE in the controller 85 yields: EQU "0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, . . . ",
which is not the original data D2 in the lockup pattern section. As a result, the data D2 in the lockup pattern section cannot be read correctly. Failing to read the data D2 correctly causes a failure to read the subsequent sync pattern data, user data in user data sections, etc.
In order to prevent the failure of data reading, the controller 85 synchronizes the data DTLE and DTTE from the two signal processors 81 and 82. In general, a lockup pattern section follows a sector mark section in a sector, so that it is possible to determine whether what is currently read is the data D2 in the lockup pattern section. Data of a sector mark recorded in a sector mark section is Burst Data, and, unlike the arrangement of other data recording areas, is characterized by a bit data arrangement under which "0" data groups and "1" data groups are alternately arranged as follows: EQU "0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, . . . ".
Therefore, even when the signal processors 81 and 82 are asynchronous, the controller 85 can still determine whether data in the sector mark section is being read out. Thus, the controller 85 can easily determine that the data to be read subsequently is the data D2 in the lockup pattern section.
When it is determined that the data obtained by synthesis of DTLE and DTTE is not the original data D2 in the lockup pattern section, the controller 85 determines which of the outputs from the two signal processors 81 and 82 is shifted and by how much it is shifted. More specifically, the controller 85 operates to shift the timing (synchronization) of data output from one of the signal processors such that a logical sum of DTLE and DTTE matches with the original data D2 in the lockup pattern section. When the logical sum becomes the original data D2 in the lockup pattern section, the controller 85 makes the determination that the data DTLE and DTTE output from the signal processors 81 and 82 is synchronized. Then, the controller 85 sequentially combines the data DTLE and DTTE.
Therefore, the data DTLE and DTTE, output from the signal processors 81 and 82 based on the signal waveform RD.sub.PWM of the data D2, are synchronized by the controller 85. Consequently, erroneous reading of data, such as sync pattern data or user data, and the failure of data reading will be avoided.
FIG. 8 schematically shows the recording format of each sector on an optical disk. Each sector 90 is generally separated into an ID section 91 and a data section 92. The ID section 91 includes a sector mark section (SM) 91a, a first lockup pattern section (first VFO) 91b, a first address mark section (first AM) 91c, a first physical address section (first ID) 91d, a second lockup pattern section (second VFO) 91e, a second address mark section (second AM) 91f, a second physical address section (second ID) 91g, and a postamble section (PA) 911. The data section 92 includes a third lockup pattern section (third VFO) 92h, a plurality of user data sections 92a, an error check code section (CRC) 92b, an error correction code section (ECC) 92c, a sync pattern section (SYNC) 92d for synchronization, a plurality of resync pattern sections (RESYNC) 92e for resynchronization, a postamble section (PA) 92f and a buffer section (BUFF) 92g.
Data D2 in a lockup pattern section, which is used for synchronization, is found in each of the VFO sections. Even after synchronization is obtained at each VFO section, the timing of the data DTLE and DTTE output from the two signal processors 81 and 82 may be unbalanced. When this is the case, synchronization cannot be obtained until a subsequent VFO section is detected, thus resulting in the disabling of data reading until synchronization can be obtained.